The invention relates to an improved method and circuit arrangement for signal processing. The invention finds particular utility in the processing of analog signals in applications where low energy consumption is of the essence. Signal processing in the present context refers to addition subtraction, integration or differentiation of voltages or, for that matter, charges or currents, that represent signals.
Processing analog signals often involves the problem of how to achieve low energy consumption as the continuous current consumption of linearly operating active analog circuits, such as e.g. operational amplifiers, is considerable.
Basic methods are known from the prior art wherein the processing of signal samples may be performed by processing the signal by means of a switching transistor that only transfers charge impulses, instead of using structures that continuously consume current. Such methods are disclosed in patent documents FI 89838 (corresponding to EP 473,436 and U.S. Pat. No. 5,387,874), FI 931831 (corresponding to EP 621,550 and U.S. Pat. No. 5,497,116) and Finnish patent document FI 101914.
Patent document FI 89838 discloses an integrating circuit wherein switches are used to control the storing in a sampling capacitor of charge samples taken from a signal voltage, and the discharging of charge samples from the sampling capacitor into an integrating capacitor. The circuit disclosed substantially consumes current only while charges are being transferred. The arrangement, however, has the drawback that it requires separate switch arrangements for the positive and negative cycles of the signal voltage as well as separate clock stages to control the switches, thus making the circuit complicated. Moreover, the use of separate circuit elements for the processing of the signal""s negative and positive cycles may result in signal distortion caused by threshold voltages and component variation.
The drawbacks of the circuit described above can be avoided by using the arrangement disclosed in patent document FI 931831. To aid in understanding the operation of the present invention and its advantages over the prior art, the operation of the circuit arrangement disclosed in said document is described below in detail with reference to FIGS. 1 to 5.
FIG. 1 shows a signal processing circuit implemented with transistors T1 and T2, in which circuit the end result is a time-discrete integral of voltage (USxe2x88x92URef). Transistors T1, T2 are N-type MOS transistors, or N-MOS transistors. Switches S21 to S30 in the circuit shown in FIG. 1 are controlled by clock signals 1 to 4. The clock signals 1 to 4 control the switches in four successive stages such that e.g. during clock stage 1 clock signal 1 sets the switches controlled by clock signal 1 into conductive state. Switches are below denoted using the letter S and indices such that the subscript refers to the switch number, which is running, and the superscript refers to the clock stages during which the switch is conductive. For example, marking S211.3 refers to switch 21 which is conductive during clock stages 1 and 3, controlled by clock signals 1 and 4. During the other clock stages 2 and 4 the switch is non-conductive. Similarly, a denotation of voltage provided with a superscript refers to the voltage appearing during the clock stage indicated by the superscript, and a denotation of charge provided with a superscript refers to the charge appearing or transferred during the clock stage indicated by the superscript. Thus, UCi2 refers to the voltage U of capacitance Ci during/at the end of clock stage 2. The clock pulses are so-called non-overlapping clock pulses, i.e. during a given stage only the switches intended to be closed during said stage are conductive, and the other switches are open.
The operation of the clock stages 1 to 4 in the circuit is described in detail in FIGS. 2 to 5, showing only those elements of the circuit of FIG. 1 that are essential from the point of view of the operation of the clock stage in question. The signs (i.e. polarities, e.g. positive or negative) of the signals and voltages are indicated relative to the ground potential.
FIG. 2 illustrates the operation during clock stage 1. Switches S21, S22, S23 and S24 are closed during clock stage 1 so that the charge-transferring capacitor Ci, here also called sampling capacitor Ci, is charged up to voltage Uci1:                               U          Ci          1                =                              U            S            1                    +                      U            Ref                    +                      U            th1                                              (        1        )            
where Uth1 is the threshold voltage of the gate-source voltage of transistor T1. When the gain of transistor T1 is large, the charge transferred to the sampling capacitor Ci comes substantially from the circuit""s supply voltage VDD and not from the signal voltage US.
The operation during the subsequent clock stage 2 is illustrated in FIG. 3. During clock stage 2, switches S26, S27 and S28 are conductive (closed) so that the sampling capacitor Ci supplies gate-source voltage to transistor T2, facilitating flow of current from the positive operating voltage VDD to the integrating capacitor CO. The current flow continues until the sampling capacitor Ci has discharged down to the threshold voltage Uth2 of the gate-source junction of transistor T2, at which point the current flow stops. So, charge is transferred from the sampling capacitor Ci to the integrating capacitor CO until the voltage of capacitor Ci has dropped to Uth2. Thus, during clock stage 2, a charge is transferred from the charge-transferring capacitor Ci to the integrating capacitor CO according to the equation:
xcex94Q2=C1(US+URefxe2x88x92Uth1xe2x88x92Uth2)xe2x80x83xe2x80x83(2) 
FIG. 4 illustrates the operation of the circuit during clock stage 3 when switches S21, S23, S24 and S25 are closed. The sampling capacitor Ci is connected to the reference voltage URef via transistor T1 so that capacitor Ci is charged up to voltage
UCi3=URefxe2x88x92Uth1xe2x80x83xe2x80x83(3) 
FIG. 5 illustrates the operation of the circuit during the last clock stage 4 when switches S26, S29 and S30 are closed. The sampling capacitor Ci supplies gate-source voltage to transistor T2 facilitating flow of current through the sampling capacitor Ci from the integrating capacitor CO to the lower operating voltage VSS. The current flow continues until the sampling capacitor Ci has discharged down to the threshold voltage Uth2 of the gate-source junction of transistor T2. The negative charge transferred to the integrating capacitor CO is then
xcex94Q4=xe2x88x92C1(URefxe2x88x92Uth1xe2x88x92Uth2)xe2x80x83xe2x80x83(4) 
When the gain of transistor T2 is large, as it is in a good bipolar transistor, or near infinite, as it is in a field-effect transistor (e.g. MOS transistor), also the charge transferred at the charge transfer stages comes from the supply voltage (VDD, VSS) and has substantially that precise magnitude which is required to transfer the desired charge from the sampling capacitance Ci to the integrating capacitance CO. The charge transferred during all clock stages 1 to 4 to the output of the circuit at the integrating capacitor CO, totals in the sum of equations (2) and (4), i.e.
xcex94Qtot=C1(Us+URefxe2x88x92Uref)=CiUSxe2x80x83xe2x80x83(5) 
Accordingly, during one cycle Tr of clock stages, i.e. during clock stages 1 to 4, the voltage of the integrating capacitor CO changes value according to equation (6):                               Δ          ⁢                      xe2x80x83                    ⁢                      U                          C              o                                      =                                                            C                i                                            C                o                                      ⁢                          (                                                U                  s                                +                                  U                  Ref                                -                                  U                  Ref                                            )                                =                                                    C                i                                            C                o                                      ⁢                          U              s                                                          (        6        )            
Thus, the circuit shown in FIG. 1 becomes a discrete-time, positive signal voltage integrating circuit the time integration weight coefficient of which is Ci/CO. The sign of the integration can be changed to negative by interchanging the order of performance of the aforementioned clock stages 2 and 4, so that the operation according to clock stage 4 is performed after stage 1, and the operation according to clock stage 2 is performed after stage 3. Consequently, the signs of the above-mentioned equations (2) and (4) and, thereby, the signs of equations (5) and (6), too, are inverted (positive becomes negative and negative becomes positive). This basic circuit may be varied according to the type of transistor used (NPN, PNP, N-MOS or P-MOS) and according to whether the circuit is to be implemented using one transistor instead of two (T1 and T2 above).
In the prior-art arrangement described above the circuit is substantially currentless after the charge transfer, and the dependence on threshold voltages and non-linearities of circuit elements is minimal. However, when realizing such a circuit using CMOS transistors, the circuit has three significant drawbacks. First, some of the switching transistors float along with the voltages processed, which in real-life implementations results in threshold voltage changes due to the so-called back-gate phenomenon. This shows as non-linearity in the operation of the circuit so that during sampling and transfer of samples a transistor may have different threshold voltages and, on the other hand, the threshold voltages may have differing values with signals of differing magnitudes. Typically, a transistor would float within one volt, approximately, whereby the threshold voltage could vary in the range of a few millivolts. Therefore, as regards the implementation of the method, it would be advantageous to minimize the variation of potential in the transistor.
Secondly, in the circuits of prior-art arrangements the way in which the transistor goes currentless is that the gate voltage drops to the threshold. This happens slowly, since the transistor""s gate voltage VGS changes through the charging of capacitance Ci, and said charging only occurs through channel resistance, which at the same time grows, approaching infinity. Thus the circuit may be slow and the growing channel resistance also causes noise.
The third drawback related to the prior-art arrangement described above is that the implementation of more than two (e.g. four) different clock signal stages complicates the circuit. Particularly in implementations integrated on silicon chips, the wiring of four clock signal stages requires a substantially greater area than the wiring of two clock stages even if the number of switches were not large. It is thus preferable to aim to minimize the number of clock signal stages required.
The drawbacks mentioned above can be partly avoided using an arrangement disclosed in patent document FI 101914. The operation of the circuit arrangement disclosed in said document is below described with the aid of FIGS. 6 to 8.
The operation of the circuit arrangement shown in FIG. 6 comprises two clock stages used to control switches S61 to S64 in the circuit. Clock signals 1 and 2 control the switches in two successive stages such that during clock stage 1 clock signal 1 sets the switches (S61, S63) controlled by clock signal 1 into conductive state. Similarly, during clock stage 2 clock signal 2 sets the switches (S62, S64) controlled by clock signal 2 into conductive state. To illustrate the operation of the circuit arrangement, FIGS. 7 and 8 separately show the elements relevant to the operation during both clock stages. The superscripts of the symbols representing switches and voltages are numerals indicating clock stages of the circuit arrangement, as in the description of FIGS. 1 to 5.
The circuit arrangement according to FIG. 6 is below described using as an example a p-channel field-effect transistor T the threshold voltage of which is VT. The magnitude of the threshold voltage VT is typically of the order of xe2x88x920.5 V. The current equations describing the operation of the p-channel FET in the region relevant to the operation of the circuit are as follows:                               I          D                =                              1            2                    ⁢                                    k              ⁡                              (                                                      V                    GS                                    -                                      V                    T                                                  )                                      2                                              (        7        )            
ID=kVDS(VGSxe2x88x92VT)xe2x80x83xe2x80x83(8) 
A constant-current element IC used in the circuit produces a substantially constant current IC. However, the operation of the circuit is first examined without the constant-current element IC. During clock stage 1 (FIG. 7) the gate G of the transistor T is connected via switch S611 to the signal voltage US and a first electrode 23 of capacitance Ci via switch S631 to constant potential Vr. A second electrode 24 of the charge-transferring capacitance Ci is connected in a fixed manner to the source S of transistor T. Thus the capacitance Ci is charged up to voltage
UC11=USxe2x88x92VTxe2x80x83xe2x80x83(9) 
Let first USxe2x89xa60 so that the absolute value of the voltage UCi of the charge-transferring capacitance is greater than the transistor""s threshold voltage VT.
During clock stage 2 (FIG. 8) the integrating capacitance CO is connected in series with the charge-transferring capacitance Ci through switch S622 and at the same time the voltage UCi of the charge-transferring capacitance Ci is connected between the source S and gate G of transistor T through switch S642. The circuit transfers charge from the supply voltage VDD until the voltage of Ci has dropped to                               U          Ci          2                =                  U          T                                    (        10        )            
The charge transferred corresponds to the voltage change of the charge-transferring capacitance Ci and its magnitude is
xcex94Q=Usxc2x7C1xe2x80x83xe2x80x83(11) 
If US greater than 0, the circuit will not operate as described above, because the voltage UCi of the charge-transferring capacitance will during both clock stages be smaller than the threshold voltage VT of transistor T and current will not flow during either clock stage. Hence the constant-current element IC in the circuit. Below it is assumed that the current IC of the constant-current element is such that the circuit has time to reach balance during each clock stage. As the value of the current of transistor T decreases or increases to value IC the current flow to the charge-transferring capacitance Ci stops, and from equations (7) and (8) we get the gate voltage corresponding to the cutoff,                               V          GS1                =                              V            T                    -                                                    I                c                                            k                ⁢                                  xe2x80x83                                ⁢                                  V                  DS                                                      ⁢                          xe2x80x83                        ⁢                          (                                                V                  T                                 less than                 0                            )                                                          (        12        )            
assuming that the transistor is operating in the linear, or triode, region. If the transistor were operating in the saturation, or pentode, region, the cutoff voltage would still be constant VT. In practice, the non-linearity according to equation (12) is caused by the fact that VDS varies to an extent comparable to the signal voltage. Since the value of the transistor-specific coefficient k is large, the distortion caused by the non-linear term is only a few millivolts at a signal voltage of 1 V so that below we can assume the current cutoff voltage to be VT. Let it be pointed out here that the transistor in FIGS. 6 to 8 is a PMOS-type transistor. With such a transistor, VT less than 0 and the transistor is conductive when VGS less than VT.
During clock stage 1, the circuit is as shown in FIG. 7 so that the charge-transferring capacitance is charged up to the voltage                               U          C1          1                =                              U            S                    -                      V            T                                              (        13        )            
If, prior to the clock stage, UC1 greater than USi xe2x88x92VT, the constant-current element discharges the capacitance Ci until UCi reaches the value of equation (13) and during that time the current through transistor T is smaller than IC. During the clock stage, the current through transistor T settles to IC and is conducted to the constant-current element IC. The current flowing to capacitance Ci is zero when the current of transistor T has stabilized to IC.
If, prior to the clock stage, UC1 less than USxe2x88x92VT, the current of transistor T rises, exceeding IC, until the voltage UCi of the charge-transferring capacitance reaches the value according to equation (7). After that, the current settles to IC which all flows to the constant-current element.
During clock stage 2 (FIG. 8) the integrating capacitance CO is connected in series with the charge-transferring capacitance Ci, and the voltage UCi of the charge-transferring capacitance, the magnitude of which is in accordance with equation (7), is connected as a control voltage for transistor T, between the gate G and source S of the transistor. If the voltage UCi=USxe2x88x92VT less than VT, transistor T is conducting more current than the value of IC to the constant-current element IC and capacitance Ci until the voltage UCi settles to VT and the current of transistor T settles to IC. If UCi=USxe2x88x92VT greater than VT, the constant-current element discharges the charge-transferring capacitance Ci until its voltage UCi reaches the value VT. During that time the current of transistor T is momentarily smaller than IC, where it settles when the charge transfer from capacitance Ci or to capacitance Ci has stopped. The charge transferred through the charge-transferring capacitance Ci is transferred to the integrating capacitance CO. The magnitude of this transferred charge is
xcex94Q=USCixe2x80x83xe2x80x83(14) 
as in equation (11), which means the circuit cell described serves as an integrator.
The above-described circuit arrangement according to FIGS. 6 to 8 involves some problems:
In filter implementations, the problem is the sensitivity of the topology to parasitic capacitances. In analog-to-digital converter applications, problems are caused by the lossiness of the self-switched charge transfer (SSCT) integrator and by signal distortion. Below it is described with the aid of FIGS. 9 and 10 how the losses and signal distortion come about.
FIG. 9 shows a circuit corresponding to that in FIG. 7 at the first clock stage such that the drawing also shows the parasitic capacitance Cp between the switches and the upper plate of the capacitor, which parasitic capacitance causes the lossiness of the integrator. In FIG. 10 the circuit is shown at the second clock stage.
At clock stage 1, FIG. 9, capacitor Cp is charged up to the reference voltage Vref. At clock stage 2, FIG. 10, the parasitic capacitance Cp is connected in parallel with integrator CO, causing the signal charge to be redistributed. The lossiness caused by the phenomenon is mathematically expressed as                               V                      o            ⁡                          (                              n                +                1                            )                                      =                                                            C                i                                                              C                  o                                +                                  C                  p                                                      ⁢                          V                              o                ⁡                                  (                  n                  )                                                              -                                                    C                i                                                              C                  o                                +                                  C                  p                                                      ⁢                          V                              i                ⁡                                  (                                      n                    +                    1                                    )                                                                                        (        15        )                                                      C            p                    =                                    1                              H                0                                      ⁢                          C              o                                      ,                              when            ⁢                          xe2x80x83                        ⁢                          C              i                                =                      C            o                                              (        16        )            
Minimization of the parasitic capacitance Cp is limited by the maximum ON resistance allowed for the switches, because the parasitic capacitance of a switching transistor can only be reduced by applying a smaller W/L (width/length) ratio, and reducing the W/L ratio increases the channel resistance. Typically, the DC gain HO of the integrator is of the order of 10 to 20.
In the known SSCT topology, the gate potential of the active transistor is changed at the different clock stages of the circuit. Thus, there is a limit to the increase of the size of the transistor based on signal distortion caused by parasitic capacitances. However, the length of the transistor has to be sufficient in order to reduce the distortion caused by channel length modulation. These contrary design parameters determine the minimum distortion of the topology.
An object of the invention is to provide an arrangement with which the afore-mentioned problems related to the prior art can be avoided.
An idea of the invention is to provide an integrator topology where the charge transfer element is preferably a source follower type transistor in which one input terminal is substantially independent of the input signal and where the essential signal path elements of the circuit topology are coupled in a fixed manner. The circuit arrangement according to the invention is preferably realized such that it comprises separate transistors for sampling and charge transfer. Thus it is possible to connect an input signal in a fixed manner to an input terminal of the sampling transistor, and an input terminal of the charge transfer transistor may be connected in a fixed manner to a constant voltage. Also, one pole of the charge-transferring capacitance and one pole of the integrating capacitance are preferably made independent of the input signal by connecting them to a constant potential. Circuit arrangements according to the invention are depicted more closely in the detailed description of the invention.
The DC gain of the new circuit topology according to the invention is more than tenfold compared to the prior-art topology, and, unlike the known topology, the circuit does not have a distortion minimum determined by mutually contradictory dimensioning principles. Moreover, the new topology enables a double operating frequency. The power supply rejection ratio is better than before, and the interaction of successive integrators is smaller than before. These changes make the topology substantially more useful e.g. in sigma-delta modulators and in filters.
Furthermore, the power consumption of the circuit topology may be reduced by means of dynamic transistor biasing. To increase the speed of SSCT cells it is advantageous to bias the active charge-transferring transistor so that the sampling rate during the positive cycle of the signal is primarily determined on the basis of the active transistor""s transconductance. During the negative signal cycle the signal settling time is determined by the transistor""s bias current. To reduce static power consumption it is advantageous to adjust the bias current dynamically on the basis of the input signal potential. The adjustment may be performed such that at the end of a clock stage the bias current is constant so that the basic assumption about the constancy of the active transistor""s gate-source voltage is true. If the sampling rate is high compared to the signal rate, the bias current may be adjusted using a sample taken during the previous clock stage. In that case the bias current may be adjusted directly in proportion to the previous sample. If the input signal changes substantially between samples, it is possible to use bias control based on the polarity of the current sample. Dynamic biasing gives about 70% savings in power consumption. The savings may be bigger if the resistance in the topology is implemented using circuits that compensate for process variation.
A method according to the invention for processing a signal, which method is comprised of steps in which
a charge-transferring capacitance is switched into functional connection with an input signal,
during the time that the charge-transferring capacitance is in functional connection with the signal, the charge of the charge-transferring capacitance is changed by a quantity of charge proportional to an instantaneous value of the signal processed,
the charge-transferring capacitance is switched into functional connection with an integrating capacitance,
during the time that the charge-transferring capacitance is in functional connection with the integrating capacitance, charge is transferred between the charge-transferring capacitance and the integrating capacitance, and
the charge of said charge-transferring capacitance is changed by means of a current generated by an active element connected to the charge-transferring capacitance, said current being dependent on the voltage of said charge-transferring capacitance,
is characterized in that
for the duration of said first and second stages one input terminal of said active element is set to a potential which is substantially independent of the input signal.
A method according to the invention for taking a sample from an input signal, in which method the input signal controls the current fed by a sampling transistor to a sampling capacitance, is characterized in that the bias of said sampling transistor is controlled at the beginning of a clock stage on the basis of the value or polarity of the input signal.
A circuit arrangement according to the invention for processing a signal, comprising
a charge-transferring capacitance,
at least one active element,
first switching elements for switching the charge-transferring capacitance into functional connection with an input signal in order to change the charge of said charge-transferring capacitance by a quantity of charge proportional to an instantaneous value of the signal,
an integrating capacitance,
second switching elements for switching the charge-transferring capacitance into functional connection with the integrating capacitance in order to transfer charge between the charge-transferring capacitance and the integrating capacitance,
at least one active element for changing the charge of the charge-transferring capacitance on the basis of the voltage of said charge-transferring capacitance, is characterized in that
one input terminal of said active element is substantially independent of the input signal.
An arrangement according to the invention for taking a sample from an input signal, which arrangement is comprised of a sampling capacitance and a sampling transistor for transferring to the sampling capacitance a charge sample proportional to the input signal, is characterized in that the arrangement comprises means for controlling the bias of the sampling transistor at the beginning of a clock stage on the basis of the value or polarity of the input signal.
Preferred embodiments of the invention are disclosed in the dependent claims.